Renesas R5S72621 User Manual
Section 37 Electrical Characteristics
Page 2018 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
37.4.7
Serial Communication Interface with FIFO Timing
Table 37.11 Serial Communication Interface with FIFO Timing
Item Symbol Min.
Max.
Unit
Figure
Input clock cycle (clocked synchronous) t
Scyc
12
t
pcyc
Figure
37.45
(asynchronous) 4
t
pcyc
Input clock rise time
t
SCKr
1.5 t
pcyc
Input clock fall time
t
SCKf
1.5 t
pcyc
Input clock width
t
SCKW
0.4
0.6
t
Scyc
Transmit data delay time
(clocked synchronous)
(clocked synchronous)
t
TXD
3
t
pcyc
15 ns
Figure
37.46
Receive data setup time
(clocked synchronous)
(clocked synchronous)
t
RXS
4
t
pcyc
15 ns
Receive data hold time
(clocked synchronous)
(clocked synchronous)
t
RXH
1
t
pcyc
15 ns
Note: t
pcyc
indicates the peripheral clock (P
) cycle.
t
SCKW
t
SCKr
t
SCKf
t
Scyc
SCK
Figure 37.45 SCK Input Clock Timing
SCK
(input/output)
TxD
(data transmit)
RxD
(data receive)
t
Scyc
t
TXD
t
RXH
t
RXS
Figure 37.46 Transmit/Receive Data Input/Output Timing
in Clocked Synchronous Mode