Renesas R5S72621 User Manual
Section 37 Electrical Characteristics
R01UH0134EJ0400 Rev. 4.00
Page 2019 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
37.4.8
Renesas Serial Peripheral Interface Timing
Table 37.12 Renesas Serial Peripheral Interface Timing
Item Symbol Min.
Max.
Unit
Figure
RSPCK clock cycle
Master
t
SPcyc
2
4096 t
cyc
Figure
37.47
37.47
Slave 8
4096
RSPCK clock high pulse width
Master
t
SPCKWH
0.4
t
SPcyc
Slave 0.4
RSPCK clock low pulse width
Master
t
SPCKWL
0.4
t
SPcyc
Slave 0.4
Data input setup time
Master
t
SU
15
ns Figures
37.48
to
37.51
to
37.51
Slave 0
t
cyc
Data input hold time
Master
t
H
0
ns
Slave 4
t
cyc
SSL setup time
Master
t
LEAD
1 8 t
SPcyc
Slave 4
t
cyc
SSL hold time
Master
t
LAG
1 8 t
SPcyc
Slave 4
t
cyc
Data output delay time
Master
t
OD
21 ns
Slave
4 t
cyc
Data output hold time
Master
t
OH
5
ns
Slave 3
t
cyc
Continuous transmission delay time
Master
t
TD
1
t
SPcyc
2 t
cyc
8
t
SPcyc
2 t
cyc
ns
Slave 4
t
cyc
Slave access time
t
SA
4 t
cyc
Figures
37.50,
37.51
37.51
Slave out release time
t
REL
3 t
cyc