Renesas R5S72621 User Manual
Section 7 Interrupt Controller
Page 166 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
7.3.3
Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to
IRQ0 individually: low level, falling edge, rising edge, or both edges.
IRQ0 individually: low level, falling edge, rising edge, or both edges.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
IRQ71S IRQ70S IRQ61S IRQ60S IRQ51S IRQ50S IRQ41S IRQ40S IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
15
IRQ71S
0
R/W
IRQ Sense Select
These bits select whether interrupt signals
corresponding to pins IRQ7 to IRQ0 are detected by a
low level, falling edge, rising edge, or both edges.
corresponding to pins IRQ7 to IRQ0 are detected by a
low level, falling edge, rising edge, or both edges.
00: Interrupt request is detected on low level of IRQn
input
01: Interrupt request is detected on falling edge of IRQn
input
10: Interrupt request is detected on rising edge of IRQn
input
11: Interrupt request is detected on both edges of IRQn
input
14 IRQ70S
0 R/W
13 IRQ61S
0 R/W
12 IRQ60S
0 R/W
11 IRQ51S
0 R/W
10 IRQ50S
0 R/W
9 IRQ41S
0 R/W
8 IRQ40S
0 R/W
7 IRQ31S
0 R/W
6 IRQ30S
0 R/W
5 IRQ21S
0 R/W
4 IRQ20S
0 R/W
3 IRQ11S
0 R/W
2 IRQ10S
0 R/W
1 IRQ01S
0 R/W
0 IRQ00S
0 R/W
[Legend]
n = 7 to 0