Renesas R5S72621 User Manual
Section 7 Interrupt Controller
R01UH0134EJ0400 Rev. 4.00
Page 173 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
7.4
Interrupt Sources
There are five types of interrupt sources: NMI, user debugging interface, IRQ, PINT, and on-chip
peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the
highest. When set to level 0, that interrupt is masked at all times.
peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the
highest. When set to level 0, that interrupt is masked at all times.
7.4.1
NMI Interrupt
1-Mbyte version
The NMI interrupt has a priority level of 16 and is accepted at all times. NMI interrupt
requests are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0
(ICR0) selects whether the rising edge or falling edge is detected.
requests are edge-detected, and the NMI edge select bit (NMIE) in interrupt control register 0
(ICR0) selects whether the rising edge or falling edge is detected.
Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets
the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.
the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.
640-Kbyte version
The NMI interrupt has a priority level of 16 and is accepted at all times when the NMI mask
bit (NMIM) in interrupt control register 0 (ICR0) is enabled. NMI interrupt requests are edge-
detected, and the NMI edge select bit (NMIE) in ICR0 selects whether the rising edge or
falling edge is detected.
bit (NMIM) in interrupt control register 0 (ICR0) is enabled. NMI interrupt requests are edge-
detected, and the NMI edge select bit (NMIE) in ICR0 selects whether the rising edge or
falling edge is detected.
Though the priority level of the NMI interrupt is 16, the NMI interrupt exception handling sets
the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.
the interrupt mask level bits (I3 to I0) in the status register (SR) to level 15.
When the NMIM bit in ICR0 is set to 1 (NMI interrupt request is masked), the NMI interrupt
is not generated, however the NMI edge corresponding to NMIE bit of ICR0 is detected and
the NMI interrupt request is retained until the interrupt request is accepted. The status of the
interrupt request can be checked by reading the NMI interrupt request bit (NMIF) in the ICR0.
If 0 is written to the NMIM bit (NMI interrupt request is enabled) when the NMIF bit is set to
1, the NMI interrupt request that is retained is accepted. Once the NMIM bit is set to 0 (NMI
interrupt request is enabled), the NMIM bit cannot be set to 1 again, because only 0 can be
written to the NMIM bit. When the NME bit is changed, the NMI interrupt request that is
retained is cleared.
is not generated, however the NMI edge corresponding to NMIE bit of ICR0 is detected and
the NMI interrupt request is retained until the interrupt request is accepted. The status of the
interrupt request can be checked by reading the NMI interrupt request bit (NMIF) in the ICR0.
If 0 is written to the NMIM bit (NMI interrupt request is enabled) when the NMIF bit is set to
1, the NMI interrupt request that is retained is accepted. Once the NMIM bit is set to 0 (NMI
interrupt request is enabled), the NMIM bit cannot be set to 1 again, because only 0 can be
written to the NMIM bit. When the NME bit is changed, the NMI interrupt request that is
retained is cleared.