Renesas R5S72621 User Manual
Section 8 Cache
R01UH0134EJ0400 Rev. 4.00
Page 221 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
8.3.4
Write Operation (Only for Operand Cache)
(1) Write Hit
In a write access in write-back mode, the data is written to the cache and no write cycle to the
external memory or the large-capacity on-chip RAM is issued. The U bit of the entry written is set
to 1 and LRU is updated so that the hit way becomes the latest.
external memory or the large-capacity on-chip RAM is issued. The U bit of the entry written is set
to 1 and LRU is updated so that the hit way becomes the latest.
In write-through mode, the data is written to the cache and a write cycle to the external memory or
the large-capacity on-chip RAM is issued. The U bit of the written entry is not updated and LRU
is updated so that the replaced way becomes the latest.
the large-capacity on-chip RAM is issued. The U bit of the written entry is not updated and LRU
is updated so that the replaced way becomes the latest.
(2) Write Miss
In write-back mode, an internal bus cycle starts when a write miss occurs, and the entry is
updated. The way to be replaced follows table 8.4. When the U bit of the entry to be replaced is 1,
the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written
to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way
becomes the latest. After the cache completes its update cycle, the write-back buffer writes the
entry back to the memory. The write-back unit is 16 bytes. Cache update operation and write-
back operation to the memory are performed in wrap-around mode. When the lower four bits of
the address of write-miss data are H'4, for example, cache update operation and write-back
operation to the memory are performed in the following order of the lower 4-bit value of address:
H'4
updated. The way to be replaced follows table 8.4. When the U bit of the entry to be replaced is 1,
the cache update cycle starts after the entry is transferred to the write-back buffer. Data is written
to the cache, the U bit is set to 1, and the V bit is set to 1. LRU is updated so that the replaced way
becomes the latest. After the cache completes its update cycle, the write-back buffer writes the
entry back to the memory. The write-back unit is 16 bytes. Cache update operation and write-
back operation to the memory are performed in wrap-around mode. When the lower four bits of
the address of write-miss data are H'4, for example, cache update operation and write-back
operation to the memory are performed in the following order of the lower 4-bit value of address:
H'4
H'8 H'C H'0.
In write-through mode, no write to cache occurs in a write miss; the write is only to the external
memory or the large-capacity on-chip RAM.
memory or the large-capacity on-chip RAM.
8.3.5
Write-Back Buffer (Only for Operand Cache)
When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to
the external memory or the large-capacity on-chip RAM. To increase performance, the entry to be
replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes
priority over writing back to the external memory. After the cache completes to fetch the new
entry, the write-back buffer writes the entry back to the external memory or the large-capacity on-
chip RAM. During the write-back cycles, the cache can be accessed. The write-back buffer can
hold one line of cache data (16 bytes) and its physical address. Figure 8.3 shows the configuration
of the write-back buffer.
the external memory or the large-capacity on-chip RAM. To increase performance, the entry to be
replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes
priority over writing back to the external memory. After the cache completes to fetch the new
entry, the write-back buffer writes the entry back to the external memory or the large-capacity on-
chip RAM. During the write-back cycles, the cache can be accessed. The write-back buffer can
hold one line of cache data (16 bytes) and its physical address. Figure 8.3 shows the configuration
of the write-back buffer.