Renesas R5S72621 User Manual
Section 8 Cache
R01UH0134EJ0400 Rev. 4.00
Page 223 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
[Legend]
x: Don't
care.
Note: Cache update cycle: 16-byte read access
Write-back cycle in write-back buffer: 16-byte write access
* Neither LRU updated. LRU is updated in all other cases.
8.3.6
Coherency of Cache and External Memory or Large-Capacity On-Chip RAM
Use software to ensure coherency between the cache and the external memory or the large-
capacity on-chip RAM. When memory shared by this LSI and another device is mapped in the
cache-enabled space, operate the memory-mapped cache to invalidate and write back as required.
The same operation should be performed for the memory shared by the CPU and the direct
memory access controller in this LSI.
capacity on-chip RAM. When memory shared by this LSI and another device is mapped in the
cache-enabled space, operate the memory-mapped cache to invalidate and write back as required.
The same operation should be performed for the memory shared by the CPU and the direct
memory access controller in this LSI.