Renesas R5S72621 User Manual
Section 8 Cache
R01UH0134EJ0400 Rev. 4.00
Page 225 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
back operation to the memory is performed in the following order of the lower 4-bit value of
address: H'0
address: H'0
H'4 H'8 H'C.
(3) Address-Array Write (Associative Operation)
When writing with the associative bit (A bit) of the address field set to 1, the addresses in the four
ways for the entry specified by the address field are compared with the tag address that is specified
by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field
to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged.
When there is no way that has a hit, nothing is written and there is no operation. This function is
used to invalidate a specific entry in the cache.
ways for the entry specified by the address field are compared with the tag address that is specified
by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field
to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged.
When there is no way that has a hit, nothing is written and there is no operation. This function is
used to invalidate a specific entry in the cache.
When the U bit of the entry that has had a hit is 1 in the operand cache, writing back should be
performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that
entry. Write-back operation to the memory is performed in the following order of the lower 4-bit
value of address: H'0
performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that
entry. Write-back operation to the memory is performed in the following order of the lower 4-bit
value of address: H'0
H'4 H'8 H'C.
8.4.2
Data Array
To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for
write accesses) must be specified. The address field specifies information for selecting the entry to
be accessed; the data field specifies the longword data to be written to the data array.
write accesses) must be specified. The address field specifies information for selecting the entry to
be accessed; the data field specifies the longword data to be written to the data array.
Specify the entry address for selecting the entry, the L bit indicating the longword position within
the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is
longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way
1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword,
specify B'00 for bits 1 and 0 of the address.
the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is
longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way
1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword,
specify B'00 for bits 1 and 0 of the address.
For the address and data formats, see figure 8.4.
The following two operations are possible for the data array. Information in the address array is
not modified by this operation.
not modified by this operation.
(1) Data Array Read
The data specified by the L bit in the address is read from the entry address specified by the
address and the entry corresponding to the way.
address and the entry corresponding to the way.