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Renesas R5S72621 User Manual

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Section 9   Bus State Controller 
 
Page 280 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
9.4.4
 
SDRAM Control Register (SDCR) 
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be 
connected. 
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
-
-
-
-
-
-
-
-
-
-
-
A2ROW[1:0]
A3ROW[1:0]
A2COL[1:0]
A3COL[1:0]
-
-
-
DEEP
SLOW
RFSH RMODEPDOWN BACTV
-
-
-
-
 
 
Bit Bit 
Name 
Initial 
Value 
R/W Description 
31 to 21 
 All 
0 
R 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
20, 19 
A2ROW[1:0]  00 
R/W 
Number of Bits of Row Address for Area 2 
Specify the number of bits of row address for area 2. 
00: 11 bits 
01: 12 bits 
10: 13 bits 
11: Reserved (setting prohibited) 
18 
 0 
R 
Reserved 
This bit is always read as 0. The write value should 
always be 0. 
17, 16 
A2COL[1:0]  00 
R/W 
Number of Bits of Column Address for Area 2 
Specify the number of bits of column address for  
area 2. 
00: 8 bits 
01: 9 bits 
10: 10 bits 
11: Reserved (setting prohibited)