Renesas R5S72621 User Manual
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00
Page 281 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
15, 14
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
13 DEEP
0 R/W
Deep
Power-Down
Mode
This bit is valid for low-power SDRAM. If the RFSH or
RMODE bit is set to 1 while this bit is set to 1, the
deep power-down entry command is issued and the
low-power SDRAM enters the deep power-down
mode.
RMODE bit is set to 1 while this bit is set to 1, the
deep power-down entry command is issued and the
low-power SDRAM enters the deep power-down
mode.
0: Self-refresh mode
1: Deep power-down mode
12 SLOW
0 R/W
Low-Frequency
Mode
Specifies the output timing of command, address, and
write data for SDRAM and the latch timing of read
data from SDRAM. Setting this bit makes the hold
time for command, address, write and read data
extended for half cycle (output or read at the falling
edge of CKIO). This mode is suitable for SDRAM with
low-frequency clock.
write data for SDRAM and the latch timing of read
data from SDRAM. Setting this bit makes the hold
time for command, address, write and read data
extended for half cycle (output or read at the falling
edge of CKIO). This mode is suitable for SDRAM with
low-frequency clock.
0: Command, address, and write data for SDRAM is
output at the rising edge of CKIO. Read data from
SDRAM is latched at the rising edge of CKIO.
SDRAM is latched at the rising edge of CKIO.
1: Command, address, and write data for SDRAM is
output at the falling edge of CKIO. Read data from
SDRAM is latched at the falling edge of CKIO.
SDRAM is latched at the falling edge of CKIO.
11 RFSH
0 R/W
Refresh
Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
SDRAM is performed.
0: No refresh
1: Refresh