Renesas R5S72621 User Manual
Section 9 Bus State Controller
Page 298 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
9.5.3
Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 1, 4, and 5 to insert wait cycles independently in read
access and in write access. Areas 0, 2, 3, and 6 have common access wait for read cycle and write
cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access
shown in figure 9.8.
WR0 in CSnWCR. It is possible for areas 1, 4, and 5 to insert wait cycles independently in read
access and in write access. Areas 0, 2, 3, and 6 have common access wait for read cycle and write
cycle. The specified number of Tw cycles are inserted as wait cycles in a normal space access
shown in figure 9.8.
T1
CKIO
A25 to A0
CSn
RD/
WR
RD
D15 to D0
WEn
D15 to D0
BS
Tw
Read
Write
T2
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only)