Renesas R5S72621 User Manual
Section 9 Bus State Controller
Page 300 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
9.5.4
CSn Assert Period Expansion
The number of cycles from
CSn assertion to RD, WEn assertion can be specified by setting bits
SW1 and SW0 in CSnWCR. The number of cycles from
RD, WEn negation to CSn negation can
be specified by setting bits HW1 and HW0. Therefore, a flexible interface to an external device
can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles,
can be obtained. Figure 9.10 shows an example. A Th cycle and a Tf cycle are added before and
after an ordinary cycle, respectively. In these cycles,
RD and WEn are not asserted, while other
signals are asserted. The data output is prolonged to the Tf cycle, and this prolongation is useful
for devices with slow writing operations.
for devices with slow writing operations.
T1
CKIO
A25 to A0
CSn
RD/
WR
RD
D15 to D0
WEn
D15 to D0
BS
Th
Read
Write
T2
DACKn*
Tf
Note: * The waveform for DACKn is when active low is specified.
Figure 9.10
CSn Assert Period Expansion