Renesas R5S72621 User Manual
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00
Page 301 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
9.5.5
MPX-I/O Interface
Access timing for the MPX space is shown below. In the MPX space,
CS5, AH, RD, and WEn
signals control the accessing. The basic access for the MPX space consists of 2 cycles of address
output followed by an access to a normal space. The bus width for the address output cycle or the
data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits
depending on the address to be accessed.
output followed by an access to a normal space. The bus width for the address output cycle or the
data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits
depending on the address to be accessed.
Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3.
Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided
without inserting idle cycles, even in continuous access cycles. Address output is increased to 3
cycles by setting the MPXW bit in CS5WCR to 1.
Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided
without inserting idle cycles, even in continuous access cycles. Address output is increased to 3
cycles by setting the MPXW bit in CS5WCR to 1.
The RD/
WR signal is output at the same time as the CS5 signal; it is high in the read cycle and
low in the write cycle.
The data cycle is the same as that in a normal space access.
The delay cycles specified by SW[1:0] are inserted between the Ta3 and T1 cycles. The delay
cycles specified by HW[1:0] are added after the T2 cycle.
cycles specified by HW[1:0] are added after the T2 cycle.
Timing charts are shown in figures 9.11 to 9.13.