Renesas R5S72621 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00
Page 515 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.4.3
Buffer Operation
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers. In channel 0, TGRF can also be used as a buffer register.
registers. In channel 0, TGRF can also be used as a buffer register.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
register or as a compare match register.
Note: TGRE_0 cannot be designated as an input capture register and can only operate as a
compare match register.
Table 11.41 shows the register combinations used in buffer operation.
Table 11.41 Register Combinations in Buffer Operation
Channel
Timer General Register Buffer
Register
0 TGRA_0
TGRC_0
TGRB_0 TGRD_0
TGRE_0 TGRF_0
3 TGRA_3
TGRC_3
TGRB_3 TGRD_3
4 TGRA_4
TGRC_4
TGRB_4 TGRD_4
When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
transferred to the timer general register.
This operation is illustrated in figure 11.14.
Buffer
register
Timer general
register
TCNT
Comparator
Compare match signal
Figure 11.14 Compare Match Buffer Operation