Renesas R5S72621 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
Page 598 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
11.7
Usage Notes
11.7.1
Module Standby Mode Setting
Operation of this module can be disabled or enabled using the standby control register. The initial
setting is for the operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 33, Power-Down Modes.
setting is for the operation to be halted. Register access is enabled by clearing module standby
mode. For details, refer to section 33, Power-Down Modes.
11.7.2
Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. This module will not operate properly at
narrower pulse widths.
least 2.5 states in the case of both-edge detection. This module will not operate properly at
narrower pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.98 shows the input clock
conditions in phase counting mode.
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.98 shows the input clock
conditions in phase counting mode.
Overlap
Phase
differ-
ence
Phase
differ-
ence
Overlap
TCLKA
(TCLKC)
(TCLKC)
TCLKB
(TCLKD)
(TCLKD)
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap
Pulse width
: 1.5 states or more
: 2.5 states or more
: 2.5 states or more
Figure 11.98 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode