Renesas R5S72621 User Manual
Section 13 Watchdog Timer
Page 664 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
13.3.2
Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and timer enable bit.
count, overflow flags, and timer enable bit.
When used to count the clock oscillation settling time for canceling software standby mode, it
retains its value after counter overflow.
retains its value after counter overflow.
Use word access to write to WTCSR, writing H'A5 in the upper byte. Use byte access to read from
WTCSR.
WTCSR.
Note: The method for writing to WTCSR differs from that for other registers to prevent
erroneous writes. See section 13.3.4, Notes on Register Access, for details.
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
R/(W)
R/W
R/W
R
R
R/W
R/W
R/W
Bit:
Initial value:
R/W:
IOVF
WT/
IT
TME
-
-
CKS[2:0]
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 IOVF 0 R/(W)
Interval
Timer
Overflow
Indicates that WTCNT has overflowed in interval
timer mode. This flag is not set in watchdog timer
mode.
timer mode. This flag is not set in watchdog timer
mode.
0: No overflow
1: WTCNT overflow in interval timer mode
[Clearing condition]
When 0 is written to IOVF after reading IOVF