Renesas R5S72621 User Manual
Section 13 Watchdog Timer
Page 666 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
2 to 0
CKS[2:0]
000
R/W
Clock Select
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (P
count from the eight types obtainable by dividing the
peripheral clock (P
). The overflow period that is
shown inside the parenthesis in the table is the value
when the peripheral clock (P
when the peripheral clock (P
) is 24 MHz.
Bits 2 to 0
Clock Ratio Overflow
Cycle
000: 1
P 10.6
s
001: 1/64
P 680
s
010: 1/128
P 1.4
ms
011: 1/256
P 2.7
ms
100: 1/512
P 5.4
ms
101: 1/1024
P 10.9
ms
110: 1/4096
P 44
ms
111: 1/16384
P 174
ms
Note: If bits CKS[2:0] are modified when this module
is running, the up-count may not be performed
correctly. Ensure that these bits are modified
only when this module is not running.
correctly. Ensure that these bits are modified
only when this module is not running.