Renesas R5S72621 User Manual
Section 13 Watchdog Timer
R01UH0134EJ0400 Rev. 4.00
Page 673 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
13.5
Usage Notes
Pay attention to the following points when using this module in either the interval timer or
watchdog timer mode.
watchdog timer mode.
13.5.1
Timer Variation
After timer operation has started, the period from the power-on reset point to the first count up
timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The
shortest such time period is thus one cycle of the peripheral clock, P
timing of WTCNT varies depending on the time period that is set by the TME bit of WTCSR. The
shortest such time period is thus one cycle of the peripheral clock, P
, while the longest is the
result of frequency division according to the value in the CKS[2:0] bits. The timing of subsequent
incrementation is in accord with the selected frequency division ratio. Accordingly, this time
difference is referred to as timer variation.
incrementation is in accord with the selected frequency division ratio. Accordingly, this time
difference is referred to as timer variation.
This also applies to the timing of the first incrementation after WTCNT has been written to during
timer operation.
timer operation.
13.5.2
Prohibition against Setting H'FF to WTCNT
When the value in WTCNT reaches H'FF, this module assumes that an overflow has occurred.
Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or reset will occur
immediately, regardless of the current clock selection by the CKS[2:0] bits.
Accordingly, when H'FF is set in WTCNT, an interval timer interrupt or reset will occur
immediately, regardless of the current clock selection by the CKS[2:0] bits.
13.5.3
Interval Timer Overflow Flag
When the value in WTCNT is H'FF, the IOVF flag in WTCSR cannot be cleared.
Only clear the IOVF flag when the value in WTCNT has either become H'00 or been changed to a
value other than H'FF.
value other than H'FF.