Renesas R5S72621 User Manual
Section 13 Watchdog Timer
Page 674 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
13.5.4
System Reset by
WDTOVF Signal
If the
WDTOVF signal is input to the RES pin of this LSI, this LSI cannot be initialized correctly.
Avoid input of the
WDTOVF signal to the RES pin of this LSI through glue logic circuits. To
reset the entire system with the
WDTOVF signal, use the circuit shown in figure 13.6.
RES
WDTOVF
Reset input
(Low active)
Reset signal to
entire system
(Low active)
Figure 13.6 Example of System Reset Circuit Using
WDTOVF Signal
13.5.5
Manual Reset in Watchdog Timer Mode
When a manual reset occurs in watchdog timer mode, the bus cycle is continued. If a manual reset
occurs while the bus is released or during burst transfer by the direct memory access controller,
manual reset exception handling will be pended until the CPU acquires the bus mastership.
occurs while the bus is released or during burst transfer by the direct memory access controller,
manual reset exception handling will be pended until the CPU acquires the bus mastership.
13.5.6
Internal Reset in Watchdog Timer Mode
When an internal reset is generated by an overflow of the watchdog timer counter (WTCNT) in
watchdog timer mode, the watchdog reset control/status register (WRCSR) is not initialized and
the WOVF bit is set to 1. When the value of the WOVF bit is 1, no internal reset is generated
when a WTCNT overflow occurs.
watchdog timer mode, the watchdog reset control/status register (WRCSR) is not initialized and
the WOVF bit is set to 1. When the value of the WOVF bit is 1, no internal reset is generated
when a WTCNT overflow occurs.