Renesas R5S72621 User Manual
Section 15 Serial Communication Interface with FIFO
R01UH0134EJ0400 Rev. 4.00
Page 715 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
15.3.1
Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RxD pin is loaded into SCRSR in the order received,
LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is
automatically transferred to the receive FIFO data register (SCFRDR).
LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is
automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit:
Initial value:
R/W:
15.3.2
Receive FIFO Data Register (SCFRDR)
SCFRDR is a 16-byte FIFO register that stores serial receive data. The reception of one byte of
serial data is complete when the received data is moved from the receive shift register (SCRSR) to
SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can
read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the
value is undefined.
serial data is complete when the received data is moved from the receive shift register (SCRSR) to
SCFRDR for storage. Continuous reception is possible until 16 bytes are stored. The CPU can
read but not write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the
value is undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W: