Renesas R5S72621 User Manual
Section 16 Renesas Serial Peripheral Interface
Page 798 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
16.3.11
Slave Select Negation Delay Register (SSLND)
SSLND sets a period (SSL negation delay) from the transmission of a final RSPCK edge to the
negation of the SSL signal during a serial transfer by this module in master mode. If the contents
of SSLND are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the
function of this module enabled in master mode, the subsequent operation cannot be guaranteed.
negation of the SSL signal during a serial transfer by this module in master mode. If the contents
of SSLND are changed while the MSTR and SPE bits in the control register (SPCR) are 1 with the
function of this module enabled in master mode, the subsequent operation cannot be guaranteed.
When using this module in slave mode, set B'000 to SLNDL2 to SLNDL0.
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
R
R
R
R
R
R/W
R/W
R/W
⎯
⎯
⎯
⎯
⎯
SLN
DL2
SLN
DL1
SLN
DL0
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 3
All
0
R
Reserved
The write value should always be 0. Otherwise,
operation cannot be guaranteed.
operation cannot be guaranteed.
2
1
0
SLNDL2
SLNDL1
SLNDL0
0
0
0
R/W
R/W
R/W
SSL Negation Delay Setting
These bits set an SSL negation delay when the
SLNDEN bit in SPCMD is 1.
SLNDEN bit in SPCMD is 1.
The relationship between the setting of SLNDL2 to
SLNDL0 and the SSL negation delay value is shown
below.
SLNDL0 and the SSL negation delay value is shown
below.
000: 1 RSPCK
001: 2 RSPCK
010: 3 RSPCK
011: 4 RSPCK
100: 5 RSPCK
101: 6 RSPCK
110: 7 RSPCK
111: 8 RSPCK