Renesas R5S72621 User Manual
Section 17 I
2
C Bus Interface 3
R01UH0134EJ0400 Rev. 4.00
Page 865 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
17.3.6
Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I
slave address. In slave mode with the I
2
C bus format, if the upper seven bits of SAR match the
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
device.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
SVA[6:0]
FS
Bit Bit
Name
Initial
Value
Value
R/W Description
7 to 1
SVA[6:0]
0000000
R/W
Slave Address
These bits set a unique address in these bits,
differing form the addresses of other slave devices
connected to the I
differing form the addresses of other slave devices
connected to the I
2
C bus.
0 FS
0 R/W
Format
Select
0: I
2
C bus format is selected
1: Clocked synchronous serial format is selected
17.3.7
I
2
C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT while transferring
data of ICDRS, continuous transfer is possible.
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT while transferring
data of ICDRS, continuous transfer is possible.
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W: