Renesas R5S72621 User Manual
Section 17 I
2
C Bus Interface 3
R01UH0134EJ0400 Rev. 4.00
Page 867 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
17.3.10
NF2CYC Register (NF2CYC)
NF2CYC is an 8-bit readable/writable register that selects a transfer clock and the range of the
noise filtering for the SCL and SDA pins. For details of the noise filter, see section 17.4.7, Noise
Filter.
noise filtering for the SCL and SDA pins. For details of the noise filter, see section 17.4.7, Noise
Filter.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R/W
R
R
R/W
R/W
Bit:
Initial value:
R/W:
-
-
-
CKS4
-
-
PRS
NF2
CYC
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
7 to 5
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
4 CKS4
0 R/W
Transfer
Clock
Select
This bit should be set according to the necessary
transfer rate (table 17.3) in master mode.
For 1-Mbyte version, this bit is reserved and always
read as 0. The write value should always be 0.
transfer rate (table 17.3) in master mode.
For 1-Mbyte version, this bit is reserved and always
read as 0. The write value should always be 0.
3, 2
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
1
PRS
0
R/W
Pulse Width Ratio Select
Specifies the ratio of the high-level period to the low-
level period for the SCL signal.
level period for the SCL signal.
0: The ratio of high to low is 0.5 to 0.5.
1: The ratio of high to low is about 0.4 to 0.6.
0
NF2CYC
0
R/W
Noise Filtering Range Select
0: The noise less than one cycle of the peripheral clock
can be filtered out
1: The noise less than two cycles of the peripheral clock
can be filtered out