Renesas R5S72621 User Manual

 

Section 17   I

2

C Bus Interface 3 

R01UH0134EJ0400  Rev. 4.00  

 

Page 869 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

In master transmit mode, the master device outputs the transmit clock and transmit data, and the 
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to 
figures 17.5 and 17.6. The transmission procedure and operations in master transmit mode are 
described below. 

1.  Set the ICE bit in ICCR1 to 1. Also, set bits CKS[3:0] in ICCR1. (Initial setting) 

2.  Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in 

ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP. (Start condition 
issued) This generates the start condition. 

3.  After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data 

show the slave address and R/

W) to ICDRT. At this time, TDRE is automatically cleared to 0, 

and data is transferred from ICDRT to ICDRS. TDRE is set again. 

4.  When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 

at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the 
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1, 
the slave device has not been acknowledged, so issue the stop condition. To issue the stop 
condition, write 0 to BBSY and SCP. SCL is fixed low until the transmit data is prepared or 
the stop condition is issued. 

5.  The transmit data after the second byte is written to ICDRT every time TDRE is set. 

6.  Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last 

byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the 
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or 
NACKF. 

7.  When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.