Renesas R5S72621 User Manual

Section 18 Serial Sound Interface

Page 910 of 2108

R01UH0134EJ0400 Rev. 4.00

Sep

24,

2014

SH7262 Group, SH7264 Group

18.3.3

Transmit Data Register (SSITDR)

SSITDR is a 32-bit register that stores data to be transmitted. The data for transmission to be
stored to SSITDR is automatically transferred from the transmit FIFO data register.

Data written to this register is transferred to the shift register upon transmission request. If the data
word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit
in SSICR.

The CPU cannot read or write data from/to SSITDR.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W:

18.3.4

Receive Data Register (SSIRDR)

SSIRDR is a 32-bit register that stores received data. The received data stored in SSIRDR is
automatically transferred to the receive FIFO data register.

Data in this register is transferred from the shift register each time data word is received. If the
data word length is less than 32 bits, the alignment is determined by the setting of the PDTA
control bit in SSICR.

The CPU cannot read or write data from/to SSIRDR.

Bit:

Initial value:

R/W:

Bit:

Initial value:

R/W: