Renesas R5S72643 User Manual

 

Section 20   Controller Area Network 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1051 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

This register is a 16-bit read/write register and specifies the Tx-Trigger Time waiting for compare 
match with Cycle Time. Only one bit is allowed to be set. Please don't set more bits than one, or 
clear all bits. 

This register may only be modified during configuration mode. The modification algorithm is 
shown in figure 20.13. 

Please note that this register is only indented for test and diagnosis. When not in test mode, this 
register must not be written to and the returned value is not guaranteed. 

  TTTSEL (Address = H'0A4) 
 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R

R

R

R

R

R

R

R

TTTSEL[14:8]

Bit:

Initial value:

R/W:

-

-

-

-

-

-

-

-

-

 

Note: Only one bit is allowed to be set. 

 

Bit 15: Reserved. The written value should always be '0' and the returned value is '0'. 

Bit 14 to 8 — Specifies the Tx-Trigger Time waiting for compare match with CYCTR The bit 14 
to 8 corresponds to Mailbox-30 to 24, respectively. 

Bits 7 to 0: Reserved. The written value should always be '0' and the returned value is '0'. 

MB24

CYCTR = TTT24 or
MBC[24] != 0x000

CYCTR = TTT25 or
MBC[25] != 0x000

CYCTR = TTT26 or
MBC[26] != 0x000

CYCTR = TTT27 or
MBC[27] != 0x000

CYCTR = TTT28 or
MBC[28] != 0x000

CYCTR = TTT29 or
MBC[29] != 0x000

MB25

MB26

reception/transmission of reference
message

CYCTR = TTT30 or MBC[30] != 0x000 or
reception of reference message

MB27

MB28

MB29

MB30

reset