IBM Intel Xeon E5504 46D1351 User Manual

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

105

This register enables various maintenance operations such as ZQ, RCOMP, etc.

These are the parameters used to set the Start Scheduler for TX clock crossing. This is 
used to send commands to the DIMMs.

The NATIVE RATIO is UCLK multiplier of BCLK = U

ALIEN RATION is DCLK multiplier of BCLK = D

PIPE DEPTH = 8 UCLK (design dependent variable)

MIN SEP DELAY = 670ps (design dependent variable, Internally this is logic delay of 
FIFO + clock skew between U and D)

TOTAL EFFECTIVE DELAY = PIPE DEPTH * UCLK PERIOD in ps + MIN SEP DELAY

DELAY FRACTION = (TOTAL EFFECTIVE DELAY * D) / (UCLK PERIOD in ps * G.C.D(U,D)

Determine OFFSET MULTIPLE using the equation 

FLOOR ((OFFSET MULTIPLE +1) / G.C.D (U,D)) > DELAY FRACTION

OFFSET VALUE = MOD (OFFSET MULTIPLE, U) <= Final answer for OFFSET MULTIPLE

12:0

RW

0

MAINT_CNTR. Value to be loaded in the maintenance counter. This counter 

sequences the rate to ZQ, RCOMP in increments of maintenance counter 

intervals.

23:16

RW

2

OFFSET. TX offset setting.

15:8

RW

1

ALIENRATIO. Dclk ratio to BCLK. TX Alien Ratio setting.

7:0

RW

4

NATIVERATIO. Uclk ratio to BCLK. TX Native Ratio setting.