IBM Intel Xeon E5504 46D1351 User Manual
Product codes
46D1351
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
107
Register Description
2.15.30 MC_CHANNEL_0_ROUND_TRIP_LATENCY
MC_CHANNEL_1_ROUND_TRIP_LATENCY
MC_CHANNEL_2_ROUND_TRIP_LATENCY
These are the parameters to set the early warning RX clock crossing the Bubble
Generator FIFO (BGF) used to go between different clocking domains. These settings
provide the gearing necessary to make that clock crossing.
Generator FIFO (BGF) used to go between different clocking domains. These settings
provide the gearing necessary to make that clock crossing.
2.15.31 MC_CHANNEL_0_PAGETABLE_PARAMS1
MC_CHANNEL_1_PAGETABLE_PARAMS1
MC_CHANNEL_2_PAGETABLE_PARAMS1
These are the parameters used to control parameters for page closing policies.
2.15.32 MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH0
MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH1
MC_TX_BG_CMD_DATA_RATIO_SETTINGS_CH2
Channel Bubble Generator ratios for CMD and DATA.
Device:
4, 5, 6
Function: 0
Offset:
D4h
Access as a Dword
Bit
Type
Reset
Value
Description
7:0
RW
0
ROUND_TRIP_LATENCY. Round trip latency for reads. Units are in UCLK. This
register must be programmed with the appropriate time for read data to be
retuned from the pads after a READ CAS is sent to the DIMMs.
Device:
4, 5, 6
Function: 0
Offset:
D8h
Access as a Dword
Bit
Type
Reset
Value
Description
15:8
RW
0
RSVD.
7:0
RW
0
ADAPTIVETIMEOUTCOUNTER. Upper 8 MSBs of a 12-bit counter. This
counter adapts the interval between assertions of the page close flag. For a less
aggressive page close, the length of the count interval is increased and vice
versa for a more aggressive page close policy.
Device:
4, 5, 6
Function: 0
Offset:
E0h
Access as a Dword
Bit
Type
Reset
Value
Description
15:8
RW
1
ALIENRATIO. DCLK to BCLK ratio.
7:0
RW
4
NATIVERATIO. UCLK to BCLK ratio.