IBM Intel Xeon E5504 46D1351 User Manual

126

 Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

• When one quad rank DIMMs is used, it must be populated in DIMM slot0 (farthest 

away from the CPU) of a given channel

• Mixing of quad ranks DIMMs (RDIMM Raw Cards F and H) in one channel and three 

DIMMs in other channel (3DPC) on the same CPU socket is not allowed. If such 
configuration is detected on a CPU socket, BIOS would flag this as a warning and 
disable the QR DIMM channel(s).

For three slot per channel configurations, the Intel 5500 platform requires DIMMs 
within a channel to be populated starting with the DIMMs farthest from the processor in 
a “fill-farthest” approach (see 

). In addition, when populating a Quad-rank 

DIMM with a Single- or Dual-rank DIMM in the same channel, the Quad-rank DIMM 
must be populated farthest from the processor. Note that Quad-rank DIMMs and 
UDIMMs are not allowed in three slots populated configurations. Intel recommends 
checking for correct DIMM placement during BIOS initialization. Additionally, Intel 
strongly recommends that all designs follow the DIMM ordering, command clock, and 
control signal routing documented in 

. This addressing must be maintained 

to be compliant with the reference BIOS code supplied by Intel. All allowed DIMM 
population configurations for three slots per channel are shown in 

.

ODT[5:4] is muxed with CS[7:6]#.

CLK:

Processor

D

I

M
M

1

4/5/6/7

2/3

D

I

M
M

2

P2/N2

2/3
4/5

Fill

Second

Fill

First

Chip Select:

ODT:

P1/N1

D

I

M
M

0

Fill

Third

0/1/2/3

0/1

P0/N0

1/3

0/2

CKE:

0/2

P3/N3 P2/N2