IBM Intel Xeon E5504 46D1351 User Manual

128

 Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

For two slot per channel configurations, the Intel 5500 platform requires DIMMs within 
a channel to be populated starting with the DIMMs farthest from the processor in a “fill-
farthest” approach (see 

). In addition, when populating a Quad-rank DIMM 

with a Single- or Dual-rank DIMM in the same channel, the Quad-rank DIMM must be 
populated farthest from the processor. Intel recommends checking for correct DIMM 
placement during BIOS initialization. Additionally, Intel strongly recommends that all 
designs follow the DIMM ordering, command clock, and control signal routing 
documented in 

. This addressing must be maintained to be compliant with 

the reference BIOS code supplied by Intel. All allowed DIMM population configurations 
for two slots per channel are shown in 

.

1. 8 GB DDR3 MetaSDRAM R-DIMM only. Designers considering the support of MetaSDRAM R-DIMM are

recommended to review the platform VR design guidelines as the DC/AC load requirement may be different

from that of RDIMM/UDIMM.

2. If a DIMM faster than the maximum supported speed is populated, BIOS will force the memory to run at the

maximum supported speed.

1

DDR3-1066

1N

Empty

Empty

Dual-rank

2

DDR3-1066

1N

Empty

Dual-rank

Dual-rank

3

DDR3-1066

1N

Dual-rank

Dual-rank

Dual-rank

CLK:

Processor

D

I

M
M

0

0/1/2/3

0/1

D

I

M
M

1

P1/N1

4/5/6/7

2/3

Chip Select:

ODT:

P0/N0

0/2

1/3

CKE:

Fill

Second

Fill

First

P3/N3

P2/N2