IBM Intel Xeon E5504 46D1351 User Manual

52

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

Number of cores, threads BIOS wants to exist on the next reset. A processor reset 
must be used for this register to take affect. Note programing this register to a value 
higher than the product has cores, should not be done. Which cores are removed is not 
defined and is implementation dependent. This does not result in all of the power 
savings of a reduced number of core product, but does save more power than even the 
deepest sleep state.

.

Status register for various Memory and Control Register functions that can be locked 
down.

16

RW1S

0

LOCK. Once written to 1, changes to this register cannot be made.

8

RWL

0

MT_DISABLE. Disables multi-threading (2 logical threads per core) in all 

cores if set to 1.

1:0

RWL

0

CORE_COUNT.
00: max number (default value)
01 - 1 core
10 - 2 cores

9

RO

-

MEM_LOCKED_REMOTE. Any access to local memory from another agent 

(i.e. everybody but this processor) is aborted. Can only be unlocked when in 

Authenticated Code Mode.

8

RO

-

MEM_LOCKED_LOCAL. Any Access to local memory from this processor is 

aborted. Can only be unlocked when in Authenticated Code Mode.

1

RO

-

MEM_CFG_USER_LOCKED. Locks same as MEM_CFG_LOCKED but user 

controlled lockable by MC_CFG_CONTROL; unlockable via MC_CFG_CONTROL 

csr(0x0090).

0

RO

-

MEM_CFG_LOCKED. All Configuration registers dealing with memory and 

address programming are locked down and cannot be changed. This includes all 

registers in Device 3 Function [0,1], Device 4,5,6 Function 0, Device 4,5,6 

Function 1, Device 4,5,6 Function 2, and most registers in Device 0 Function 1. 

But does not include the memory controller thermal registers, or 

SAD_PAM0123, SAD_PAM456, SAD_SMRAM registers.