IBM Intel Xeon E5504 46D1351 User Manual

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Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

Status Register reporting the current Uncore Clk Ratio relative to BCLK (133Mhz). This 
is the clock in which the Last Level Cache (LLC) runs. 

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RO

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MISCV. IA32_MC7_MISC. Register Valid Flag. Indicates (when set) that 

the IA32_MC7_MISC register contains additional information regarding the 
error. When clear, this flag indicates that the IA32_MC7_MISC register is 

either not implemented or does not contain additional information regarding 

the error. Do not read these registers if they are not implemented in the 

processor.

58

RO

-

.

 Register Valid Flag. Indicates (when set) that 

the IA32_MC7_ADDR register contains the address where the error occurred. 

When clear , this flag indicates that the IA32_MC7_ADDR register is either 

not implemented or does not contain the address where the error occurred. 

Do not read these registers if they are not implemented in the processor.

57

RO

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PCC. Processor context corrupt flag. Indicates (when set) that the state of 

the processor might have been corrupted by the error condition detected 
and that reliable restarting of the processor may not be possible. When 

cleared, this flag indicates that the error did not affect the processor’s state.

0: Not Corrupt
1: Corrupt

56:32

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31:16

RO

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MODEL SPECIFIC ERROR CODE. Specifies the model specific error code 

that uniquely identifies the machine-check error condition detected. The 

following list describes the error codes that may be found on the processor.

0x0000: No Error
0x0300: Unexpected reset error.  Processor boot failed.
0x0800: PMReq or CmpD received was illegal in the current context.
0x0A00: Illegal PMReq request detected under S3, S4 or S5.
0x0D00: Invalid S-state transition requested.
0x1100: Platform / CPU VID controller mismatch.  Processor boot failed.
0x1A00: Platform / CPU MSID mismatch.  Processor boot failed.
0x2000: QPI training error.

15:0

RO

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MCA ERROR CODE FIELD. Specifies the machine-check architecture-

defined error code for the machine-check error condition detected. The 

machine-check architecture-defined error codes are guaranteed to be the 

same for all IA-32 processors that implement the machine-check 

architecture.

See Section 14.7 of the Software Developers Manual, Vol 3A, “Interpreting 

the MCA Error Codes,” and Appendix E, “Interpreting Machine-Check Error 

Codes”, for information on machine-check error codes.

15

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0

RSVD.

14:8

RW

12

RSVD.

6:0

RO

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UCLK. The current UCLK ratio