IBM Intel Xeon E5504 46D1351 User Manual

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

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System Management Interrupt control register.

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DIMM_ERROR_OVERFLOW_STATUS. This 12-bit field is the per dimm error 

overflow status bits. The organization is as follows:
If there are three or more DIMMS on the channel:
Bit 0 : Dimm 0 Channel 0 
Bit 1 : Dimm 1 Channel 0 
Bit 2 : Dimm 2 Channel 0 
Bit 3 : Dimm 3 Channel 0 
Bit 4 : Dimm 0 Channel 1 
Bit 5 : Dimm 1 Channel 1 
Bit 6 : Dimm 2 Channel 1 
Bit 7 : Dimm 3 Channel 1 
Bit 8 : Dimm 0 Channel 2 
Bit 9 : Dimm 1 Channel 2 
Bit 10 : Dimm 2 Channel 2 
Bit 11 : Dimm 3 Channel 2

If there are one or two DIMMS on the channel: 
Bit 0 : Dimm 0, Ranks 0 and 1, Channel 0 
Bit 1 : Dimm 0, Ranks 2 and 3, Channel 0 
Bit 2 : Dimm 1, Ranks 0 and 1, Channel 0 
Bit 3 : Dimm 1, Ranks 2 and 3, Channel 0 
Bit 4 : Dimm 0, Ranks 0 and 1, Channel 1 
Bit 5 : Dimm 0, Ranks 2 and 3, Channel 1 
Bit 6 : Dimm 1, Ranks 0 and 1, Channel 1 
Bit 7 : Dimm 1, Ranks 2 and 3, Channel 1 
Bit 8 : Dimm 0, Ranks 0 and 1, Channel 2 
Bit 9 : Dimm 0, Ranks 2 and 3, Channel 2 
Bit 10 : Dimm 1, Ranks 0 and 1, Channel 2 
Bit 11 : Dimm 1, Ranks 2 and 3, Channel 2

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INTERRUPT_SELECT_NMI. NMI enable. Set to enable NMI signaling. Clear to 

disable NMI signaling. If both NMI and SMI enable bits are set, then only SMI is 

sent.

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INTERRUPT_SELECT_SMI. SMI enable. Set to enable SMI signaling. Clear to 

disable SMI signaling. If both NMI and SMI enable bits are set, then only SMI is 

sent. This bit functions the same way in Mirror and Independent Modes.
The possible SMI events enabled by this bit are: 
Any one of the error counters MC_COR_ECC_CNT_X meets the value of 

SMI_ERROR_THRESHOLD field of this register.

MC_RAS_STATUS.REDUNDANCY_LOSS bit is set to 1.

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SMI_ERROR_THRESHOLD. Defines the error threshold to compare against 

the per-DIMM error counters MC_COR_ECC_CNT_X, which are also 15 bits.