IBM Intel Xeon E5504 46D1351 User Manual

Product codes
46D1351
Page of 130
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
77
Register Description
2.11.7
MC_MAX_DOD
Defines the MAX number of DIMMS, RANKS, BANKS, ROWS, COLS among all DIMMS 
populating the three channels. The Memory Init logic uses this register to cycle through 
all the memory addresses writing all 0's to initialize all locations. This register is also 
used for scrubbing and must always be programmed if any DODs are programmed.
2.11.8
MC_RD_CRDT_INIT
These registers contain the initial read credits available for issuing memory reads. TAD 
read credit counters are loaded with the corresponding values at reset and anytime this 
register is written. BIOS must initialize this register with appropriate values depending 
on the level of Isoch support in the platform. It is illegal to write this register while TAD 
is active (has memory requests outstanding), as the write will break TAD's outstanding 
credit count values. 
Register programming rules:
• Total read credits (CRDT_RD + CRDT_RD_HIGH + CRDT_RD_CRIT) must not 
exceed 31.
• CRDT_RD_HIGH value must correspond to the number of high RTIDs reserved at 
the IOH.
• CRDT_RD_CRIT value must correspond to the number of critical RTIDs reserved at 
the IOH.
Device:
3
Function: 0
Offset:
64h
Access as a Dword
Bit
Type
Reset
Value
Description
10:9
RW
0
MAXNUMCOL. Maximum Number of Columns.
00: 2^10 columns
01: 2^11 columns
10: 2^12 columns
11: RSVD.
8:6
RW
0
MAXNUMROW. Maximum Number of Rows.
000: 2^12 Rows
001: 2^13 Rows
010: 2^14 Rows
011: 2^15 Rows
100: 2^16 Rows
Others: RSVD.
5:4
RW
0
MAXNUMBANK. Max Number of Banks.
00: Four-banked
01: Eight-banked
10: Sixteen-banked.
3:2
RW
0
MAXNUMRANK. Maximum Number of Ranks.
00: Single Ranked
01: Double Ranked
10: Quad Ranked.
1:0
RW
0
MAXNUMDIMMS. Maximum Number of Dimms.
00: 1 Dimm
01: 2 Dimms
10: 3 Dimms
11: RSVD.