IBM Intel Xeon E5504 46D1351 User Manual
Product codes
46D1351
Register Description
88
Intel® Xeon® Processor 5500 Series Datasheet, Volume 2
2.15
Integrated Memory Controller Channel Control
Registers
2.15.1
MC_CHANNEL_0_DIMM_RESET_CMD
MC_CHANNEL_1_DIMM_RESET_CMD
MC_CHANNEL_2_DIMM_RESET_CMD
Integrated Memory Controller DIMM reset command register. This register is used to
sequence the reset signals to the DIMMs.
sequence the reset signals to the DIMMs.
2.15.2
MC_CHANNEL_0_DIMM_INIT_CMD
MC_CHANNEL_1_DIMM_INIT_CMD
MC_CHANNEL_2_DIMM_INIT_CMD
Integrated Memory Controller DIMM initialization command register. This register is
used to sequence the channel through the physical layer training required for DDR.
used to sequence the channel through the physical layer training required for DDR.
Device:
4, 5, 6
Function: 0
Offset:
50h
Access as a Dword
Bit
Type
Reset
Value
Description
2
RW
0
BLOCK_CKE. When set, CKE will be forced to be deasserted.
1
RW
0
ASSERT_RESET. When set, Reset will be driven to the DIMMs.
0
WO
0
RESET. Reset the DIMMs. Setting this bit will cause the Integrated Memory
Controller DIMM Reset state machine to sequence through the reset sequence
using the parameters in MC_DIMM_INIT_PARAMS.
Device:
4, 5, 6
Function: 0
Offset:
54h
Access as a Dword
Bit
Type
Reset
Value
Description
17
WO
0
ASSERT_CKE. When set, all CKE will be asserted. Write a 0 to this bit to stop
the init block from driving CKE. This bit has no effect once
MC_CONTROL.INIT_DONE is set. This bit must be used during INITIALIZATION
only and be cleared out before MC_CONTROL.INIT_DONE is set. This bit must
not be asserted during initialization for S3 resume.
16
RW
0
DO_RCOMP. When set, an RCOMP will be issued to the rank specified in the
RANK field.
15
RW
0
DO_ZQCL. When set, a ZQCL will be issued to the rank specified in the RANK
field.
14
RW
0
WRDQDQS_MASK. When set, the Write DQ-DQS training will be skipped.
13
RW
0
WRLEVEL_MASK. When set, the Write Levelization step will be skipped.
12
RW
0
RDDQDQS_MASK. When set, the Read DQ-DQS step will be skipped.
11
RW
0
RCVEN_MASK. When set, the RCVEN step will be skipped.
10
WO
0
RESET_FIFOS. When set, the TX and RX FIFO pointers will be reset at the next
BCLK edge. The Bubble Generators will also be reset.
9
RW
0
IGNORE_RX. When set, the read return datapath will ignore all data coming
from the RX FIFOS. This is done by gating the early valid bit.
8
RW
0
STOP_ON_FAIL. When set along with the AUTORESETDIS not being set, the
phyinit FSM will stop if a step has not completed after timing out.