IBM Intel Xeon E5504 46D1351 User Manual

90

Intel® Xeon® Processor 5500 Series Datasheet, Volume 2

26

RW

0

DIS_3T. When set, 3T mode will not be enabled as a part of the MRS write to 

the RDIMM. The RC2 write to switch to 3T and back to 1T timing before and 

after an MRS write will not be done if the bit is set. This bit should be set if the 

RDIMM supports auto MRS cycles where the dimm takes care of the 3T 

switching on MRS writes. 

25

RW

0

DIS_AI. When set, address inversion will not be disabled as a part of the MRS 

write to the RDIMM. The RC0 write to disable and enable address inversion will 

not be done. This bit should be set if the RDIMM supports auto MRS cycles 

where the dimm takes care of disabling address inversion for MRS writes.

24

RW

0

THREE_DIMMS_PRESENT. Set when channel contains three DIMMs. 

THREE_DIMMS_PRESENT=1 and QUAD_RANK_PRESENT=1 (or 

SINGLE_QUAD_RANK_PRESENT=1) are mutually exclusive.

23

RW

0

SINGLE_QUAD_RANK_PRESENT. Set when channel contains a single quad 

rank DIMM.

22

RW

0

QUAD_RANK_PRESENT. Set when channel contains 1 or 2 quad rank DIMMs.

21:17

RW

15

WRDQDQS_DELAY. Specifies the delay in DCLKs between reads and writes for 

WRDQDQS training.

16

RW

0

WRLEVEL_DELAY. Specifies the delay used between write CAS indications for 

write leveling training.
0: 16 DCLKs.
1: 32 DCLKs.

15

RW

0

REGISTERED_DIMM. Set when channel contains registered DIMMs.

14:10

RW

0

PHY_FSM_DELAY. Global timer used for bounding the physical layer training. 

If the timer expires, the FSM will go to the next step and the counter will be 

reloaded with PHY_FSM_DELAY value. Units are 2^n dclk.

9:5

RW

0

BLOCK_CKE_DELAY. Delay in ns from when clocks and command are valid to 

the point CKE is allowed to be asserted. Units are in 2^n uclk.

4:0

RW

0

RESET_ON_TIME. Reset will be asserted for the time specified. Units are 2^n 

Uclk.