Intel X5460 AT80574KJ087N Data Sheet

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BCLK[1:0]

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The differential bus clock pair BCLK[1:0] (Bus Clock) determines the 

FSB frequency. All processor FSB agents must receive these signals 

to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising 

edge of BCLK0 crossing V

CROSS

.

3

BINIT#

I/O

BINIT# (Bus Initialization) may be observed and driven by all 

processor FSB agents and if used, must connect the appropriate pins 

of all such agents. If the BINIT# driver is enabled during power on 

configuration, BINIT# is asserted to signal any bus condition that 

prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration (see 

) and BINIT# is sampled asserted, symmetric agents 

reset their bus LOCK# activity and bus request arbitration state 

machines. The bus agents do not reset their I/O Queue (IOQ) and 

transaction tracking state machines upon observation of BINIT# 

assertion. Once the BINIT# assertion has been observed, the bus 

agents will re-arbitrate for the FSB and attempt completion of their 

bus queue and IOQ entries.
If BINIT# observation is disabled during power-on configuration, a 

priority agent may handle an assertion of BINIT# as appropriate to 

the error handling architecture of the system.

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BNR#

I/O

BNR# (Block Next Request) is used to assert a bus stall by any bus 

agent who is unable to accept new bus transactions. During a bus 

stall, the current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same 

time, BNR# is a wired-OR signal which must connect the appropriate 

pins of all processor FSB agents. In order to avoid wired-OR glitches 

associated with simultaneous edge transitions driven by multiple 

drivers, BNR# is activated on specific clock edges and sampled on 

specific clock edges.

3

BPM5#
BPM4# 
BPM3#
BPM[2:1]#
BPM0#

I/O

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I/O

O

I/O

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance 

monitor signals. They are outputs from the processor which indicate 

the status of breakpoints and programmable counters used for 

monitoring processor performance. BPM[5:0]# should connect the 

appropriate pins of all FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. 

PRDY# is a processor output used by debug tools to determine 

processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP 

port. PREQ# is used by debug tools to request debug operation of the 

processors.
BPM[5:4]# must be bussed to all bus agents. Please refer to the 

appropriate platform design guidelines for more detailed information.

2

BPMb3#
BPMb[2:1]#
BPMb0#

I/O

O

I/O

BPMb[3:0]# (Breakpoint Monitor) are breakpoint and performance 

monitor signals. They are outputs from the processor which indicate 

the status of breakpoints and programmable counters used for 

monitoring processor performance. BPMb[3:0]# should connect the 

appropriate pins of all FSB agents.

BPRI#

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BPRI# (Bus Priority Request) is used to arbitrate for ownership of the 

processor FSB. It must connect the appropriate pins of all processor 

FSB agents. Observing BPRI# active (as asserted by the priority 

agent) causes all other agents to stop issuing new requests, unless 

such requests are part of an ongoing locked operation. The priority 

agent keeps BPRI# asserted until all of its requests are completed, 

then releases the bus by deasserting BPRI#.

3

BR[1:0]#

I/O

The BR[1:0]# signals are sampled on the active-to-inactive transition 

of RESET#. The signal which the agent samples asserted determines 

its agent ID. BR0# drives the BREQ0# signal in the system and is 

used by the processor to request the bus. 
These signals do not have on-die termination and must be 

terminated.

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