Intel X5460 AT80574KJ087N Data Sheet

74

DEFER#

I

DEFER# is asserted by an agent to indicate that a transaction cannot 

be guaranteed in-order completion. Assertion of DEFER# is normally 

the responsibility of the addressed memory or I/O agent. This signal 

must connect the appropriate pins of all processor FSB agents.

3

DP[3:0]#

I/O

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# 

signals. They are driven by the agent responsible for driving 

D[63:0]#, and must connect the appropriate pins of all processor 

FSB agents.

3

DRDY#

I/O

DRDY# (Data Ready) is asserted by the data driver on each data 

transfer, indicating valid data on the data bus. In a multi-common 

clock data transfer, DRDY# may be deasserted to insert idle clocks. 

This signal must connect the appropriate pins of all processor FSB 

agents.

3

DSTBN[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

3

DSTBP[3:0]#

I/O

Data strobe used to latch in D[63:0]#.

3

FERR#/PBE#

O

FERR#/PBE# (floating-point error/pending break event) is a 

multiplexed signal and its meaning is qualified by STPCLK#. When 

STPCLK# is not asserted, FERR#/PBE# indicates a floating-point 

error and will be asserted when the processor detects an unmasked 

floating-point error. When STPCLK# is not asserted, FERR#/PBE# is 

similar to the ERROR# signal on the Intel387 coprocessor, and is 

included for compatibility with systems using MS-DOS*-type floating-

point error reporting. When STPCLK# is asserted, an assertion of 

FERR#/PBE# indicates that the processor has a pending break event 

waiting for service. The assertion of FERR#/PBE# indicates that the 

processor should be returned to the Normal state. For additional 

information on the pending break event functionality, including the 

identification of support of the feature and enable/disable 

information, refer to Vol. 3 of the Intel

Software Developer’s Manual and the Intel Processor Identification 

and the CPUID Instruction application note.

2

FORCEPR#

I

The FORCEPR# (force power reduction) input can be used by the 

platform to cause the Quad-Core Intel® Xeon® Processor 5400 

Series to activate the Thermal Control Circuit (TCC).

GTLREF_ADD_MID
GTLREF_ADD_END

I

GTLREF_ADD determines the signal reference level for AGTL+ 

address and common clock input lands. GTLREF_ADD is used by the 

AGTL+ receivers to determine if a signal is a logical 0 or a logical 1. 

Please refer to 

 and the appropriate platform design 

guidelines for additional details.

D[15:0]#, DBI0#

DSTBN0#

D[31:16]#, DBI1#

DSTBN1#

D[47:32]#, DBI2#

DSTBN2#

D[63:48]#, DBI3#

DSTBN3#

D[15:0]#, DBI0#

DSTBP0#

D[31:16]#, DBI1#

DSTBP1#

D[47:32]#, DBI2#

DSTBP2#

D[63:48]#, DBI3#

DSTBP3#