Intel Xeon E7330 LF80565QH0566M Data Sheet
Product codes
LF80565QH0566M
Electrical Specifications
42
Document Number: 318080-002
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing
Voltage (V
CROSS
). PWRGOOD is referenced to BCLK0 rising edge at 0.5 * V
TT
.
3.
These signals may be driven asynchronously.
4.
Refer to
for additional timing requirements for entering and leaving low power states.
5.
A minimum pulse width of 500 µs is recommended when FORCEPR# is asserted by the system
6.
Refer to the PWRGOOD signal definition in
for more details information on behavior of the signal.
7.
Length of assertion for PROCHOT# does not equal TCC activation time. Time is required after the assertion
and before the deassertion of PROCHOT# for the processor to enable or disable the TCC.
8.
Intel recommends the V
TT
power supply also be removed upon assertion of THERMTRIP#.
9.
This specification requires that the VID and BSEL signals be sampled no earlier than 10 μs after V
CC
(at
V
CC_BOOT
voltage) and V
TT
are stable.
10. Parameter must be measured after applicable voltage level is stable. “Stable” means that the power supply
is in regulation as defined by the minimum and maximum DC/AC specifications for all components being
powered by it.
11. The maximum PWRGOOD rise time specification denotes the slowest allowable rise time for the processor.
Measured between (0.3* V
TT
) and (0.7*V
TT
).
12. See
for BCLK specifications.
Notes:
1.
Before the clock that de-asserts RESET#
2.
After the clock that de-asserts RESET#.
Table 2-22. Miscellaneous GTL+ AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2, 3, 4
T35: Asynchronous GTL+ input pulse width
30
ns
5
T36: PWRGOOD assertion to RESET# de-assertion
1
10
ms
T37: BCLK stable to PWRGOOD assertion
10
BCLKs
6,12
T38: PROCHOT# pulse width
500
µs
7
T39: THERMTRIP# assertion until V
CC
removed
500
ms
8
T40: FERR# valid delay from STPCLK# deassertion
0
5
BCLKs
T41: V
CC
stable to PWRGOOD assertion
0.05
500
ms
10
T42: PWRGOOD rise time
20
ns
11
T43: V
CC_BOOT
stable to VID / BSEL valid
10
µs
9,10
T44: VID / BSEL valid to V
CC
stable
100
µs
10
T48: V
TT
stable to VID / BSEL valid
10
µs
10
T49: V
CCPLL
stable to PWRGOOD assertion
1
ms
10
Table 2-23. Front Side Bus AC Specifications (Reset Conditions)
T# Parameter
Min
Max
Unit
Figure
Notes
T45: Reset Configuration Signals
(A[39:3]#, BR[1:0]#, INIT#, SMI#) Setup Time
480
µs
1
T46: Reset Configuration Signals
(A[39:3]#, INIT#, SMI#) Hold Time
2
20
BCLKs
2
T47: Reset Configuration Signals
BR[1:0]# Hold Time
2
2
BCLKs
2
Table 2-24. TAP Signal Group AC Specifications (Sheet 1 of 2)
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2, 8
T55: TCK Period
30
ns
3
T56: TDI, TMS Setup Time
7.5
ns
4,7