Intel Xeon E7330 LF80565QH0566M Data Sheet
Product codes
LF80565QH0566M
Electrical Specifications
44
Document Number: 318080-002
Notes:
1.
See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for addition information.
2.
Platform support for VID transitions is required for the processor to operate within specifications.
Notes:
1.
These parameters are based on design characterization and are not tested.
2.
All AC timings for the SMBus signals are referenced at V
IL_MAX
or V
IL_MIN
and measured at the
processor pins. Refer to
.
3.
Rise time is measured from (V
IL_MAX
- 0.15V) to (V
IH_MIN
+ 0.15V). Fall time is measured
from (0.9 * SM_VCC) to (V
IL_MAX
4.
Minimum time allowed between request cycles.
5.
Following a write transaction, an internal write cycle time of 10ms must be allowed before
starting the next transaction.
Table 2-25. VID Signal Group AC Specifications
T # Parameter
Min
Max
Unit
Figure
Notes
1, 2
T80: VID Step Time
5
µs
T81: VID Dwell Time at 266.666 MHz FSB
500
µs
T82: VID Down Transition to Valid V
CC
(min)
0
µs
T83: VID Up Transition to Valid V
CC
(min)
50
µs
T84: VID Down Transition to Valid V
CC
(max)
50
µs
T85: VID Up Transition to Valid V
CC
(max)
0
µs
Table 2-26. SMBus Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes 1, 2
T90: SM_CLK Frequency
10
100
KHz
T91: SM_CLK Period
10
100
µs
T92: SM_CLK High Time
4.0
N/A
µs
T93: SM_CLK Low Time
4.7
N/A
µs
T94: SMBus Rise Time
0.02
1.0
µs
3
T95: SMBus Fall Time
0.02
0.3
µs
3
T96: SMBus Output Valid Delay
0.1
4.5
µs
T97: SMBus Input Setup Time
250
N/A
ns
T98: SMBus Input Hold Time
300
N/A
ns
T99: Bus Free Time
4.7
N/A
µs
4, 5
T100: Hold Time after Repeated Start Condition
4.0
N/A
µs
T101: Repeated Start Condition Setup Time
4.7
N/A
µs
T102: Stop Condition Setup Time
4.0
N/A
µs