Intel Core™ i7-860 Processor (8M Cache, 2.80 GHz) BX8060517860 User Manual

Datasheet

47

This register provides Intel QPI Link Control.

The registers in this section apply only to processors supporting registered DIMMs.

This register is the Primary control register.

21

RW

0

L1_MASTER 
Indicates that this end of the link is the L1 master. This link transmitter bit is an 

L1 power state master and can initiate an L1 power state transition. If this bit is 

not set, then the link transmitter is an L1 power state slave and should respond 

to L1 transitions with an ACK or NACK.
If the link power state of L1 is enabled, then there is one master and one slave 

per link. The master may only issue single L1 requests, while the slave can only 

issue single L1_Ack or L1_NAck responses for the corresponding request.

20

RW

0

L1_ENABLE 
Enables L1 mode at the transmitter. This bit should be ANDed with the receive 

L1 capability bit received during parameter exchange to determine if a 

transmitter is allowed to enter into L1. This is NOT a bit that determines the 

capability of a device. 

18

RW

0

L0S_ENABLE 
Enables L0s mode at the transmitter. This bit should be ANDed with the receive 

L0s capability bit received during parameter exchange to determine if a 

transmitter is allowed to enter into L0s. This is NOT a bit that determines the 

capability of a device. 

10

RW

0

CHANNEL2_ACTIVE 
When set, indicates MC channel 2 is active. This bit is controlled (set/reset) 

by software only. This bit is required to be set for any active channel when 

INIT_DONE is set by software.

9

RW

0

CHANNEL1_ACTIVE 
When set, indicates MC channel 1 is active. This bit is controlled (set/reset) 

by software only. This bit is required to be set for any active channel when 

INIT_DONE is set by software. Channel 0 AND Channel 1 active must both be 

set for a lockstep or mirrored pair.