Intel Core™ i7-860 Processor (8M Cache, 2.80 GHz) BX8060517860 User Manual

Datasheet

71

This register contains parameters that specify the CKE timings. All units are in DCLK.

This register contains parameters that specify ZQ timing. All units are DCLK unless 
otherwise specified. The register encodings are specified where applicable.

31:24

RW

0

tRANKIDLE. 
Rank will go into powerdown after it has been idle for the specified number of 

dclks. tRANKIDLE covers max(txxxPDEN). Minimum value is tWRAPDEN. If CKE 

is being shared between ranks then both ranks must be idle for this amount of 

time. A Power Down Entry command will be requested for a rank after this 

number of DCLKs if no request to the rank is in the MC.

23:21

RW

0

tXP. 
Minimum delay from exit power down with DLL and any valid command. Exit 

Precharge Power Down with DLL frozen to commands not requiring a locked 

DLL. Slow exit precharge powerdown is not supported. 

20:11

RW

0

tXSDLL. 
Minimum delay between the exit of self refresh and commands that require a 

locked DLL.

10:3

RW

0

tXS. 
Minimum delay between the exit of self refresh and commands not requiring a 

DLL. 

2:0

RW

0

tCKE. 
CKE minimum pulse width.

30

RW

1

Parallel_ZQ. 
Enable ZQ calibration to different ranks in parallel.

29

RW

1

tZQenable. 
Enable the issuing of periodic ZQCS calibration commands.

28:8

RW

16410

ZQ_Interval. 
Nominal interval between periodic ZQ calibration in increments of tREFI.

7:5

RW

4

tZQCS. 
This field specifies ZQCS cycles in increments of 16. This is the minimum delay 

between ZQCS and any other command. This register should be programmed to 

at least 64/16=4='100' to conform to the DDR3 specification.

4:0

RW

0

tZQInit. 
This field specifies ZQInit cycles in increments of 32. This is the minimum delay 

between ZQCL and any other command. This register should be programmed to 

at least 512/32=16='10000' to conform to the DDR3 specification.