Intel Core™ i7-860 Processor (8M Cache, 2.80 GHz) BX8060517860 User Manual

82

Datasheet

This register contains mask bits for the memory controller and specifies at which ECC 
bit(s) the error injection should occur. Any bits set to a 1 will flip the corresponding ECC 
bit. Correctable errors can be injected by flipping 1 bit or the bits within a symbol pair 
(2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or 23:16 and 31:24). Flipping bits 
in two symbol pairs will cause an uncorrectable error to be injected.

This register contains the control bits for the actual ECC error injection. This register 
needs to be written after writing into MC_CHANNEL_X_ECC_ERROR_MASK. The 
INJECT_ECC bit must be set to enable error injection. Otherwise, no error injection will 
take place even if the criteria programmed in the MC_CHANNEL_X_ADDR_MATCH 
register is met.

31:0

RW

0

ECCMASK. 
This field contains the 32 bits of MC ECC mask bit for half cacheline.

4

RW

0

INJECT_ADDR_PARITY. 
1 = Forces Address Parity error injection. Bit will reset after the first injection 

unless REPEAT_EN is set.

3

RW

0

INJECT_ECC. 
1 = Forces ECC error injection. Bit will reset after the first injection unless 

REPEAT_EN is set.

2:1

RW

0

MASK_HALF_CACHELINE.
11 = Inject the ECC code word for full cacheline.
10 = Inject the ECC code word for upper 32B half cacheline.
01 = Inject the ECC code word for lower 32B half cacheline.
00 = No masking will be applied.

0

RW

0

REPEAT_EN. 
1 = ECC errors will be injected on the channel until the bit is cleared.