Intel Core™ i7-860 Processor (8M Cache, 2.80 GHz) BX8060517860 User Manual

Datasheet

83

The usage model is to program the MC_CHANNEL_X_ADDR_MATCH and 
MC_CHANNEL_X_ECC_ERROR_MASK registers before writing the command in 
MC_CHANNEL_X_ECC_ERROR_INJECT register. When writing the 
MC_CHANNEL_X_ECC_ERROR_INJECT register, the REPEAT_EN and 
MASK_HALF_CACHELINE bits need to be set to the desired values.

To turn off the feature, write 0 to the MC_CHANNEL_X_ECC_ERROR_INJECT register.

Address parity error injection and ECC error injection can be done either at the same 
time or independently. They will both use the same MATCH settings if both are enabled.

Along with the INJECT_ECC bit set, software must generate the memory traffic that 

matches the address location programmed in the MC_CHANNEL_X_ADDR_MATCH 

register as described above in order for an error injection to take place. Unless the 

REPEAT_EN bit is set in the MC_CHANNEL_X_ECC_ERROR_INJECT register, the 

memory controller will only inject the error to the first location that matches the criteria 

programmed in the MC_CHANNEL_X_ADDR_MATCH register.

Errors are injected on writes only. Reads will be required to detect the errors in the 
MC_COR_ECC_CNT_X registers. Additionally, all writes used to inject errors must be 
committed to memory to ensure the error is detected on subsequent reads.