Intel SC5650BCDP User Manual
Intel
®
Server System SC5650BCDP TPS
Power Sub-System
Revision 1.5
Intel order number: E80367-002
25
Figure 9. Output Voltage Timing
Table 24. Turn On / Off Timing
Item
Description
Minimum
Maximum
Units
T
sb_on_delay
Delay from AC being applied to 5VSB being within
regulation.
regulation.
1500
msec
T
ac_on_delay
Delay from AC being applied to all output voltages being
within regulation.
within regulation.
2500
msec
T
vout_holdup
Time all output voltages stay within regulation after loss of
AC.
AC.
21
msec
T
pwok_holdup
Delay from loss of AC to de-assertion of PWOK.
20
msec
T
pson_on_delay
Delay from PSON
#
active to output voltages within regulation
limits.
5 400
msec
T
pson_pwok
Delay from PSON
#
deactive to PWOK being de-asserted.
50
msec
T
pwok_on
Delay from output voltages within regulation limits to PWOK
asserted at turn on.
asserted at turn on.
100 1000
msec
T
pwok_off
Delay from PWOK de-asserted to output voltages (3.3V, 5V,
12V, -12V) dropping out of regulation limits.
12V, -12V) dropping out of regulation limits.
1 200
msec
T
pwok_low
Duration of PWOK being in the de-asserted state during an
off/on cycle using AC or the PSON signal.
off/on cycle using AC or the PSON signal.
100
msec
T
sb_vout
Delay from 5VSB being in regulation to O/Ps being in
regulation at AC turn on.
regulation at AC turn on.
50 1000
msec
T
5VSB_holdup
Time the 5VSB output voltage stays within regulation after
loss of AC.
loss of AC.
70
msec
Vout
10%
Vout
Vout
T
vout rise
T
vout_on
T
vout_off
V1
V2
V3
V4