Intel SC5650BCDP User Manual

Page of 71
Power Sub-System 
Intel
®
 Server System SC5650BCDP TPS 
 
Intel order number: E80367-002 
Revision 1.5 
 
24 
Table 22. Ripple and Noise 
+3.3V 
+5V 
+12V(1,2,3,4) 
-12V 
+5VSB 
50mVp-p 50mVp-p  120mVp-p 120mVp-p 50mVp-p 
 
3.1.5.13 
Timing Requirements 
The timing requirements for power supply operation are as follows. The output voltages must 
rise from 10% to within regulation limits (T
vout_rise
) within 5 to 70ms, except for 5VSB which is 
allowed to rise from 1.0 to 25ms. The +3.3V, +5V and +12V output voltages start to rise at 
approximately the same timeAll outputs must rise monotonically. The 5V output needs to be 
greater than the +3.3V output during any point of the voltage rise. The +5V output must never 
be greater than the +3.3V output by more than 2.25V. Each output voltage reaches regulation 
within 50ms (T
vout_on
) of each other during turn on of the power supply. Each output voltage falls 
out of regulation within 400msec (T
vout_off
) of each other during turn off. The following table 
shows the timing requirements for the power supply being turned on and off via the AC input, 
with PSON held low and the PSON signal, with the AC input applied. 
Table 23. Output Voltage Timing 
Item 
Description 
Minimum 
Maximum 
Units 
T
vout_rise
 
Output voltage rise time from each main output. 
5.0* 
70* 
msec 
T
vout_on
 
All main outputs must be within regulation of each 
other within this time. 
 50 
msec 
vout_off
 
All main outputs must leave regulation within this 
time. 
 400 
msec 
* The 5VSB output voltage rise time shall be from 1.0 ms to 25 ms