Intel SC5650BCDP User Manual
Power Sub-System
Intel
®
Server System SC5650BCDP TPS
Intel order number: E80367-002
Revision 1.5
28
3.1.7.3
PSON# Input Signal
The PSON
#
signal is required to remotely turn on/off the power supply. PSON
#
is an active low
signal that turns on the +3.3V, +5V, +12V, and -12V power rails. When this signal is not pulled
low by the system, or left open, the outputs (except the +5VSB) turn off. This signal is pulled to
a standby voltage by a pull-up resistor internal to the power supply. Refer to the following table
and figure for PSON# signal characteristics.
low by the system, or left open, the outputs (except the +5VSB) turn off. This signal is pulled to
a standby voltage by a pull-up resistor internal to the power supply. Refer to the following table
and figure for PSON# signal characteristics.
Table 27. PSON# Signal Characteristics
Signal Type
Accepts an open collector/drain input from the system.
Pull-up to 5V located in power supply.
Pull-up to 5V located in power supply.
PSON
#
= Low
ON
PSON
#
= High or Open
OFF
MIN MAX
Logic level low (power supply ON)
0V
1.0V
Logic level high (power supply OFF)
2.1V
5.25V
Source current, Vpson = low
4mA
Power up delay: T
pson_on_delay
5msec
400msec
PWOK delay: T
pson_pwok
50msec
Figure 11. PSON# Required Signal Characteristics
3.1.7.4
PWOK (Power OK) Output Signal
PWOK is a power OK signal and is pulled HIGH by the power supply to indicate that all the
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when AC power has been removed for a time sufficiently long so that the
power supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state.
The start of the PWOK delay time is inhibited as long as any power supply output is within
current limit.
outputs are within the regulation limits of the power supply. When any output voltage falls below
regulation limits or when AC power has been removed for a time sufficiently long so that the
power supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state.
The start of the PWOK delay time is inhibited as long as any power supply output is within
current limit.
Table 28. PWOK Signal Characteristics
≤ 1.0 V
PS is
enabled
≥ 2.0 V
PS is
disabled
1.0V
2.0V
Enabled
Disabled
0.3V ≤ Hysterisis ≤ 1.0V
In 1.0-2.0V input voltages range is required
In 1.0-2.0V input voltages range is required
5.25V
0V