Transcend 1GB, 64Mx8, CL5, DIMM 240pin, DDR2, 667, ECC Unbuffered JM388Q643A-6 User Manual
Product codes
JM388Q643A-6
J
J
J
M
M
M
3
3
3
8
8
8
8
8
8
Q
Q
Q
6
6
6
4
4
4
3
3
3
A
A
A
-
-
-
6
6
6
240PIN DDR2 667 Unbuffered DIMM
1GB With 64Mx8 CL5
Transcend Information Inc.
7
Input AC Logic Level
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.250
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
VREF - 0.250
V
AC Input Test Condition
Condition
Symbol
Value
Unit
Note
Input reference voltage
V
REF
0.5*VDDQ
V
1
Input signal maximum peak to peak swing
V
SWING
(
MAX
) 1.0
V
1
Input signal minimum slew rate
SLEW
1.0 V/ns 2,3
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the
device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising
edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure.
Note:
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions
and VIH(AC) to VIL(AC) on the negative transitions.
and VIH(AC) to VIL(AC) on the negative transitions.
V
SWING(MAX)
delta TF
delta TR
VDD
V
IH
(AC)
min
V
IH
(DC)
min
VREF
V
IL
(DC)
max
V
IL
(AC)
max
VSS
Falling Slew= V
REF
-V
IL
(AC)
max
delta TF
Rising Slew= V
IH
(AC)
min-
V
REF
delta TR
AC Input Test Signal Waveform
Input/Output Capacitance
(V
DD
= 1.8V, V
DDQ
= 1.8V, T
A
= 25
°C)
Parameter
Symbol
Min
Max
Unit
Input capacitance (CK0 and /CK0)
Input capacitance (CK1 and /CK1)
Input capacitance (CK2 and /CK2)
Input capacitance (CKE and /CS)
Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)
Input capacitance (DQ, DM, DQS, /DQS)
CCK0
CCK1
CCK2
CI
1
CI
2
CIO
-
-
-
-
-
-
26
28
28
42
42
9
pF
pF
pF
pF
pF
pF
Note: DM is internally loaded to match DQ and DQS identically.