Transcend 1GB, 64Mx8, CL5, DIMM 240pin, DDR2, 667, ECC Unbuffered JM388Q643A-6 User Manual
Product codes
JM388Q643A-6
J
J
J
M
M
M
3
3
3
8
8
8
8
8
8
Q
Q
Q
6
6
6
4
4
4
3
3
3
A
A
A
-
-
-
6
6
6
240PIN DDR2 667 Unbuffered DIMM
1GB With 64Mx8 CL5
Transcend Information Inc.
8
Timing Parameters & Specifications
(These AC characteristics were tested on the Component)
Parameter
Symbol
Min
Max
Unit
Note
DQ output access time from CK & /CK
tAC
-450 +450
ps
DQS output access time from CK & /CK
tDQSCK
-400
+400
ps
CK high-level width
tCH 0.45
0.55 tCK
CK low-level width
tCL
0.45
0.55
tCK
CK half period
tHP min(tCL,tCH)
X
ps
Clock cycle time, CL=x
tCK 3000 8000 ps
DQ and DM input hold time
tDH 175
x ps
DQ and DM input setup time
tDS 100
X ps
Control & Address input pulse width for each input
tIPW 0.6
x tCK
DQ and DM input pulse width for each input
tDIPW 0.35
X
tCK
Data-out high-impedance time from CK/CK
tHZ X tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2* tACmin
tACmax
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ X
240 ps
DQ hold skew factor
tQHS X
340 ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
X
ps
Write command to first DQS latching transition
tDQSS WL-0.25 WL+0.25 tCK
DQS input high pulse width
tDQSH 0.35
X
tCK
DQS input low pulse width
tDQSL 0.35
X
tCK
DQS falling edge to CK setup time
tDSS
0.2 X
tCK
DQS falling edge hold time from CK
tDSH 0.2
X tCK
Mode register set command cycle time
tMRD 2
X tCK
Write postamble
tWPST 0.4
0.6 tCK
Write preamble
tWPRE 0.35
X
tCK
Address and control input hold time
tIH 275
X ps
Address and control input setup time
tIS 200
X ps
Read preamble
tRPRE 0.9
1.1 tCK
Read postamble
tRPST 0.4
0.6 tCK
Active to active command period for 1KB page size
products
products
tRRD 7.5
X
ns
Active to active command period for 2KB page size
products
products
tRRD 10
X ns
Four Activate Window for 1KB page size products
tFAW 37.5
ns