Intel Xeon X3460 BX80605X3460 User Manual

100

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

12

RO 

0

Received Target Abort
This bit is set when a device experiences a completor abort condition on a 

transaction it mastered on the primary interface (Integrated I/O internal 

bus). Note that certain errors might be detected right at the PCI Express 

interface and those transactions might not ‘propagate’ to the primary 

interface before the error is detected (for example, accesses to memory 

above VTCSRBASE). Such errors do not cause this bit to be set, and are 

reported using the PCI Express interface error bits (secondary status 

register). Conditions that cause Bit 12 to be set, include:

• Device receives a completion on the primary interface (internal bus of 

Integrated I/O) with completor abort completion Status. This includes 

CA status received on the primary side of a PCI Express port on peer-

to-peer completions also. 

• Accesses to Intel QuickPath InterConnect that return a failed completion 

status

• Other completer abort conditions detected on the Integrated 

I/O internal bus

11

RO

0

Signaled Target Abort
This bit is set when a device signals a completer abort completion status on 

the primary side (internal bus of Integrated I/O). This condition includes a 

PCI Express port forwarding a completer abort status received on a 

completion from the secondary side and passed to the primary side on a 

peer-to-peer completion.

10:9

RO

0h

DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.

8

RO

0

Master Data Parity Error
This bit is set by a device if the Parity Error Response bit in the PCI 

Command register is set and it receives a completion with poisoned data 

from the primary side or if it forwards a packet with data (including MSI 

writes) to the primary side with poison.

7

RO

0

Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.

6

RO

0

5

RO

0

66-MHz Capable
Not applicable to PCI Express. Hardwired to 0.

4

RO

1b(F:0/1/2) 

0b (F3)

Capabilities List
This bit indicates the presence of a capabilities list structure.

3

RO

0

INTx Status
Indicates that a legacy INTx interrupt condition is pending internally. This 

bit has meaning only in the legacy interrupt mode. This bit is always 0 when 

MSI-X has been selected for DMA interrupts. 
Note that the setting of the INTx status bit is independent of the INTx 

enable bit in the PCI command register that is, this bit is set anytime the 

DMA engine is setup by its driver to generate any interrupt and the 

condition that triggers the interrupt has occurred, regardless of whether a 

legacy interrupt message was signaled to the PCH or not. Note that the INTx 

enable bit has to be set in the PCICMD register for DMA to generate a INTx 

message to the PCH.
This bit is not applicable to PCI Express and DMI ports.

2:0

RV

0h