Intel Xeon X3460 BX80605X3460 User Manual
Product codes
BX80605X3460
Processor Integrated I/O (IIO) Configuration Registers
102
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.4.2.8
HDR—Header Type Register
This register identifies the header layout of the configuration space.
3.4.2.9
SVID—Subsystem Vendor ID
3.4.2.10
SID—Subsystem Device ID
3.4.2.11
CAPPTR—Capability Pointer
The CAPPTR provides the offset to the location of the first device capability in the
capability list.
capability list.
Register: HDR
Device:
8
Function: 0-3
Offset:
0Eh
Bit
Attr
Default
Description
7
RO
1b
Multi-function Device
This bit is set to 0 for Single Function Devices and 1 for multi- function
This bit is set to 0 for Single Function Devices and 1 for multi- function
devices.
6:0
RO
00h
Configuration Layout
This field identifies the format of the configuration header layout. Type1 for all
This field identifies the format of the configuration header layout. Type1 for all
PCI Express* ports and Type 0 for DMI devices.
Register:
SVID
Device:
8
Function: 0-3
Offset:
2Ch
Bit
Attr
Default
Description
7:0
RWO
0h
Subsystem Vendor Identification
This field is programmed during boot-up to indicate the vendor of the system
This field is programmed during boot-up to indicate the vendor of the system
board. After it has been written once, it becomes read only.
Register:
SID
Device: 8
Function: 0-3
Offset:
2Eh
Bit
Attr
Default
Description
7:0
RWO
00h
Subsystem Identification Number
Assigned by the subsystem vendor to uniquely identify the subsystem.
Assigned by the subsystem vendor to uniquely identify the subsystem.
Register: CAPPTR
Device:
8
Function: 0-3
Offset:
34h
Bit
Attr
Default
Description
7:0
RO
40h: F 0/1/2
00h: F 3
Capability Pointer Points to the first capability structure for the device.